Artificial intelligence is progressing ever faster with new applications and results that would not be possible only a few years ago. At the same time, hardware security is becoming increasingly important for embedded systems applications where the number of such applications keeps on growing. The connection between AI and hardware security is becoming more prominent. Today, there are numerous applications where AI has either an offensive or defensive role for HW security. AIHWS aims to position itself in the intersection of these topics and provide a space where ideas converge into exciting new approaches for HW security. This workshop will provide an environment for researchers from academic and industrial domains to discuss findings and on-going work on all aspects of hardware security and artificial intelligence including design, attacks, manufacturing, testing, validation, utilization.
We encourage researchers working on all aspects of AI and HW security to take the opportunity and use AIHWS to share their work and participate in discussions.
The authors are invited to submit the papers using
EasyChair submission system through submission link
Every accepted paper must have at least one author registered for the workshop. All submissions must follow the original LNCS format with a page limit of 18 pages, including references and possible appendices. Papers should be submitted electronically in PDF format. The post-proceedings will be published by Springer in the LNCS series.
The best workshop paper award is selected from all workshops. Each workshop nominates a candidate paper, and the winning paper is selected among them.
EXTENDED submission deadline!
Workshop paper submission deadline: Apr 1, 2023
previously Mar 15, 2023
Workshop paper notification: Apr 19, 2023
Camera-ready papers for pre-proceedings: May 1, 2023
Workshop date: June 19, 2023
(in parallel with the main conference)
The impending threat of large-scale quantum computers to classical RSA and ECC-based public-key cryptographic schemes prompted NIST to initiate a global level standardization process for Post-Quantum Cryptography (PQC). Three out of the four winning schemes are based on hard problems over structured lattices, known as lattice-based cryptographic schemes. This talk will highlight practical Side-Channel Analysis (SCA) vulnerabilities in lattice-based cryptographic cryptography, with particular focus on Kyber. In several cases, the attacker only requires minimal or almost no knowledge of the implementation to mount such practical attacks. Identified vulnerabilities can also target few protected implementations. Finally, we motivate more research towards the development of efficient and secure countermeasures for real-world security of lattice-based schemes.
Dr. Shivam Bhasin is a Senior Research Scientist and Programme Manager (Cryptographic Engineering) at Centre for Hardware Assurance, Temasek Laboratories, Nanyang Technological University Singapore. He received his PhD in Electronics & Communication from Telecom Paristech in 2011, Advanced Master in Security of Integrated Systems & Applications from Mines Saint-Etienne, France in 2008. Before NTU, Shivam held position of Research Engineer in Institut Mines-Telecom, France. He was also a visiting researcher at UCL, Belgium (2011) and Kobe University (2013). His research interests include embedded security, trusted computing and secure designs. He has co-authored several publications at recognized journals and conferences. Some of his research now also forms a part of ISO/IEC 17825 standard.
Security failure in computing systems has become one of today’s biggest concern. The primary threat is the fact that modern computing architectures –from computational optimizations to storage elements and interfaces, from end-user applications to the operating system and hypervisor, and from microarchitecture to underlying hardware– may hide unexpected vulnerabilities. This concern is gaining further momentum, with the spectacular aggressiveness of Spectre, Meltdown, and ZombieLoad vulnerabilities. Even worse, the many undocumented parts of modern architectures open doors for yet undescribed side-channel attacks. This talk discusses the problem of these vulnerabilities at the intersection of software and hardware to envision if Secure-by-Design computing is possible for future hardware architectures, where we strike a balance between security and hard-earned performance benefits. During this talk we will talk about phenomenon of several storage and computation-based attacks, their assessment & mitigations. Toward the end, we will discuss a way forward for raising the bars high enough for attackers to reach Secure-by-Design computing for future architectures.
Maria Mushtaq is an Associate Professor at Telecom Paris. She received her PhD in Information Security from the University of South Brittany, France, in 2019. She has worked as a CNRS Postdoctoral Researcher at LIRMM, University of Montpellier, France. She possesses expertise in microarchitectural vulnerability assessment and design & development of runtime mitigation solutions against side- and covert-channel information leakage in modern computing systems. Her research interests mainly focus on cryptanalysis, constructing and validating software security components, and constructing OS-based security primitives against various hardware vulnerabilities. She is currently involved in various national and international projects and has co-authored several peer-reviewed publications in international conferences and journals. She serves as program committee in several security conferences, organiser at MICSEC Winter School and General chair at PROOFS workshop, co-located with CHES.
The program starts at 10:00 am, JST (Japan Standard Time: UTC + 9h).
|09:45 - 10:00||Welcome|
|10:00 - 11:00||Keynote talk 1: A Look into Side-Channel Vulnerabilities in Lattice-Based Post-Quantum Cryptography
Shivam Bhasin, Nanyang Technological University, Singapore
|11:00 - 11:30||Coffee break|
|11:30 - 12:00||Using Model Optimization as Countermeasure against Model Recovery Attacks
Dirmanto Jap and Shivam Bhasin
|12:00 - 12:30||SoK: Assisted Fault Simulation - Existing Challenges and Opportunities Offered by AI
Asmita Adhikary and Ileana Buhan
|12:00 - 14:00||Lunch break|
|14:00 - 15:00||Keynote talk 2: Side Channel Information Leakage - The Night is Dark and Full of Terrors
Maria Mushtaq, Telecom Paris, France
|15:00 - 15:30||Hide and Seek: Using Occlusion Techniques for Side-Channel Leakage Attribution in CNNs
Thomas Schamberger, Maximilian Egger and Lars Tebelmann
|15:30 - 16:00||Secret Key Recovery Attack on Masked and Shuffled Implementations of CRYSTALS-Kyber and Saber
Linus Backlund, Kalle Ngo, Joel Gärtner and Elena Dubrova
|16:00 - 16:15||Coffee break|
|16:15 - 16:45||A Comparison of Multi-task learning and Single-task learning Approaches
Thomas Marquet and Elisabeth Oswald
|16:45 - 17:00||Farewell|
Luca Mariot, University of Twente, The Netherlands
Fatemeh Ganji, Worcester Polytechnic Institute, USA
Kostas Papagiannopoulos, University of Amsterdam, The Netherlands
Lichao Wu, Radboud University, The Netherlands
Ileana Buhan, Radboud University, The Netherlands
Guilherme Perin, Leiden University, The Netherlands
Alan Jović, University of Zagreb, Croatia
Shivam Bhasin, Nanyang Technological University, Singapore
Elena Dubrova, KTH Royal Institute of Technology, Sweden
Lukasz Chmielewski, Masaryk University, Czech Republic
Dirmanto Jap, Nanyang Technological University, Singapore
Naofumi Homma, Tohoku University, Japan
Vincent Verneuil, NXP Semiconductors, Germany
Marina Krček, TU Delft, The Netherlands